In electronic data processing (EDP) systems, including data communications systems, the data signals and the address signals are transmitted (or clocked) through the circuitry in accordance with signals from a clock signal generator. In other words, some timing standard is provided to insure the system that signals passing therethrough will pass through the logic circuitry, i.e., AND gates, NAND gates, OR gates, NOR gates, and into and out of RAMS, etc. without being "out of step," for instance, without being present at a circuit before or after a necessary control signal arrives. While electronic data processing systems are identified as synchronous systems or asynchronous systems, both types of systems operate to be in step with a basic clock signal. In a synchronous system, machine cycles in which the system accomplishes some program step, or the like, are uniform. Such an arrangement can be preferable in that normally less hardware is required than is required in an asynchronous system because the data flow in a synchronous system is designed to operate within a uniform cycle. In other words, a synchronous system is not burdened with the hardware which is necessary to handle a number of options. However, such a synchronous system can be burdensome if the user is desirous of taking advantage of high speeds and the speed of accessing the information, or the speed of data transmission, varies from one component used in the system to another component used in the system. Asynchronous systems are better able to take advantage of varying response times. The present invention takes advantage of working with a synchronous system (therefore the advantage of working with a lesser amount of hardware) but provides a means for varying the cycle time to accommodate the fact that certain components function faster, or not so fast, as certain other components used in the system.